Up to two DPUs for deeper processing
DPU-equipped systems carry one or two Marvell OCTEON data processing units inside the chassis. Each has eight Arm Neoverse N2 cores at 2.5 GHz and 16 GB of DDR5 memory, expandable to 48 GB.
Every DPU connects to the switching ASIC over a 100G internal path and to the CPU over PCIe. It works on mirrored and brokered traffic without taking a front-panel port, and you manage it from the same packet broker Web UI as the ASIC.
- Reduce
- De-duplication that can ignore TTL, MAC, DSCP, IPID, FCS and TCP sequence or checksum fields. Truncation down to network and transport headers.
- Decrypt and reassemble
- SSL decryption. TCP out-of-order reassembly in both directions. IP fragment reassembly for outer and inner fragments.
- De-identify
- Remove identifying data from packets before they reach recording and analysis tools.
- Match
- Fixed-offset signature matching, full-packet offset range matching and dynamic front-section pattern matching.
- Export flows
- NetFlow v5, NetFlow v9, IPFIX and sFlow, sampled by 5-tuple or rule at a ratio you set. Load-balance or duplicate the export across collectors.
- Stamp and rewrite
- Timestamping with PTP precision and outer MAC address modification.
- Run your own code
- An open DPU environment with Arm64 Linux, containers and DPDK/VPP for your own packet-processing functions.